1. Field of the Invention
The present invention relates to a reconfigurable logic circuit.
2. Related Art
In recent years, active studies have been made to develop spin electronics devices that utilize the degree of freedom of electron spin. An increasing number of developments based on tunnel magnetoresistance (TMR) are being made, and such developments are now being applied to magnetic random access memories, reproduction heads for hard disk drives (HDD), and the likes. Furthermore, attention is drawn to spin transistors that combine semiconductors and magnetic materials.
Typical examples of suggested spin transistors include a diffusion spin transistor (also known as a Mark Johnson type), a spin orbit control spin transistor (also known as a Supriyo Datta type), a spin-valve transistor, a single-electron spin transistor, and a resonant spin transistor.
There has also been a suggested spin transistor of a MOS structure that has the source and drain made of a magnetic material, and has a point contact formed between the channel and the drain. This point contact is of such a size as to cause a quantum effect for spin-polarized electrons, and has much higher resistance than the channel resistance. The interface resistance between the channel and the drain is the principal factor to determine the magnetization dependency of the drain current. Accordingly, with this spin transistor, a higher magnetoresistance ratio (MR ratio) can be achieved.
Further, there is a suggested reconfigurable logic circuit that includes combinations of MRAMs and MOSFETs forming basic logic gates such as AND gates and OR gates. By changing the storage state of each MRAM with the use of those basic logic gates, the reconfigurable logic circuit can control the validity or invalidity of those logic gates. In a reconfigurable logic circuit, changes can be made to the logics of the circuits after the hardware is formed. Accordingly, defects can be eliminated, and a learning function can be provided by reconfiguring the logic circuits.
One of the reconfigurable logic circuits developed on the basis of today's semiconductor techniques is an integrated circuit called a FPGA (Field Programmable Gate Array). The FPGA stores information in internal SRAM memories. In accordance with the contents of the information stored in the memories, the FPGA controls the logics and wire connections of the reconfigurable logic circuit. As the logics can be changed by software, changes can be made to the circuits after the hardware is formed. Accordingly, this technique is now increasingly used so as to produce increasingly-sophisticated integrated circuits at lower costs on short notice.
A look-up table circuit is a circuit that has logics stored in memories, and generates an output in accordance with the contents stored in the memories. A logic circuit including such a look-up table circuit is a reconfigurable logic circuit that can cope with any logic. However, since such a logic circuit includes a large number of elements, it is difficult to achieve high integration with the use of such logic circuits (see JP-A 2007-184959 (KOKAI) and U.S. Pat. No. 7,019,557).
In a case where a look-up table circuit is to be produced by a semiconductor CMOS technique, SRAMs are used as the memory to store information. As a result, the number of elements in the look-up table circuit becomes large. Also, the multiplexer used in such a look-up table circuit requires a large number of elements. Therefore, the circuit size of the look-up table circuit becomes very large, and becomes one of the factors that hinder high integration. Furthermore, SRAMS are volatile memories that lose information when the power supply is switched off, and it is necessary to write the information stored in an external memory, every time the power supply is switched on. This leads to the troublesome and time-consuming process required at the time of power activation. It is also necessary to secure the external memory to store information when the power supply is switched off, and larger power consumption and capacity are required for the external memory. This is one of the factors that hinder high integration and a reduction of power consumption in the entire system.
In a case of a 4-to-1 look-up table circuit that is normally used in a FPGA, the number of elements is approximately 166. Among the elements, the SRAMs account for approximately 96 elements. A look-up table circuit is an essential circuit in each FPGA. Therefore, if the number of elements in each look-up table circuit included in large numbers in a chip is reduced, higher integration can be realized.